Top

previous chapter Building and Deployment

next chapter System on Programmable Chip (SOPC)

Hint

Swipe to navigate through the chapters of this book

2016 | OriginalPaper | Chapter

9. Field-Programmable Gate Arrays

Author: Changyi Gu

Publisher: Apress

Published in: Building Embedded Systems

» Get access to the full version

Abstract

Now comes the “hard” part. The next three chapters are all about hardware, which covers a wide gamut of topics like FPGA, SOPC, LCD, etc. This chapter begins with an overview of the embedded hardware in general, followed by detailed discussions about FPGA and IP protection.

Please log in to get access to this content

To get access to this content you need the following product:

Computer Science Explorer

Purchase now

So far there are still no systematic approaches to reliably verify or prove the correctness of asynchronous design.

For example, process(all) is not supported by Modelsim until version 10.0.

For the sake of one-hot encoding, a reversed case statement is adopted where 1'b1 is put in the case expression. A reverse case statement is good for synthesis because only the active FF is compared instead of the whole vector (Ref [ 10]).

In Verilog 2001, wildcard is supported by using always @(*). In VHDL 2008, it is supported by using process(all).

Note that metal case/DIP is not the only package available. The oscillator could be in any package, such as a plastic case with a surface mount package.

The solution described here mainly applies to Altera FPGAs. But I guess similar setups can be found for devices from other FPGA vendors.

“Crossing the abyss: asynchronous signals in a synchronous world.” Mike Stein, Paradigm Works, EDN Magazine, July, 24, 2003

“Practical design for transferring signals between clock domains.” Michael Crews and Yong Yuenyongsgool, Philips Semiconductors, EDN Magazine, February, 20, 2003

Simulation and Synthesis Techniques for Asynchronous FIFO Design, Rev 1.2, Clifford E. Cummings, Sunburst Design, Inc., SNUG (Synopsys User Group Conference), San Jose, 2002

Verilog Digital Computer Design - Algorithms into Hardware. Mark Gordon Arnold, University of Wyoming, Prentice Hall PTR, 1999

Verilog HDL Synthesis - A Practical Primer. J. Bhasker, Bell Labs, Lucent Technologies, Star Galaxy Publishing, 1998

Verilog Digital System Design, Zainalabedin Navabi, Northeastern University, University of Tehran, McGraw-Hill, 1999

The Designer's Guide to VHDL, Third Edition., Peter J. Ashenden, Morgan Kaufmamn Publishers Inc., May 2008

Designing with FPGAs & CPLDs. Bob Zeidman, CMP Book, 2002

Verilog Designer's Library. Bob Zeidman, Prentice Hall PTR, 1999

10.

SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling (Second Edition). Stuart Sutherland, Simon Davidmann, and Peter Flake, Springer Science+Business Media, October, 2010

11.

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features (Second Edition). Chris Spear, Springer Science+Business Media, November, 2010

12.

“Microcontroller Oscillator Circuit Design Considerations.” Cathy Cox and Clay Merritt, Freescale Semiconductor, 2004

13.

TCXO Application vs OCXO Application (Application Notes #803, REV 1), Dave Kenny, PLETRONICS

14.

“Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever know which to use?”. Clifford E. Cummings and Don Mills, SNUG (Synopsys Users Group), San Jose, 2002

15.

“Asynchronous & Synchronous Reset Design Techniques - Part Deux.” Clifford E. Cummings, Don Mills, Steve Golson, SNUG Boston 2003

16.

Area-Time Complexity for VLSI, C. D. Thompson, Carnegie-Mellon University, CALTECH CONFERENCE ON VLSI, January, 1979

17.

Some Area-Time Tradeoffs for VLSI, Richard P. Brent and Leslie M. Goldschlager, SIAM (Society for Industrial and Applied Mathematics) J. Comput., Vol. 11, No. 4, November, 1982

18.

FPGA implementation of a DSP Core for Full Rate and Half Rate GSM Vocoders, Hamid Noori, Hossein Pedram, Ahmad Akbari, Shervin Sheidaei, The 12th International Conference on Microelectronics, Tehran, October 31 - November 2, 2000

19.

LVDS SERDES Transmitter/Receiver ( ALTLVDS_TX and ALTLVDS_RX) IP Cores User Guide, Altera Corp, December, 2014

20.

The Art of PCB Reverse Engineering: Unraveling the Beauty of the Original Design, by Mr. Keng Tiong Ng, CreateSpace Independent Publishing Platform, February, 2015

21.

ModelSim User’s Manual, Software Version 10.1c, Mentor Graphics Corporation, 2012

22.

Thicket(TM) Family of Source Code Obfuscators, Sematic Designs, Incorporated ( http://www.semdesigns.com )

23.

HDL Code Obfuscation (Tcl Script), Aldec Inc. ( https://www.aldec.com )

24.

Quartus Prime Standard Edition Handbook Volume 1: Design and Synthesis, Altera Corporation, May 4, 2015

25.

Synopsys FPGA Synthesis Synplify Pro for Microsemi Edition - User Guide, Synopsys, Inc. February, 2013

26.

AN 593: Anti-Tamper Protection for Cyclone III LS Devices, Altera Corporation, October, 2009

27.

MAX 10 FPGA Configuration User Guide, Altera Corporation, December 14, 2015

28.

White Paper: Anti-Tamper Capabilities in FPGA Designs, Ver 1.0, Altera Corporation July, 2008

29.

Omron D2FS Ultra Subminiature Anti-Tamper Switch, OMRON Corporation, 2013

30.

AN528: Buried Capacitive Sensors for Tamper Protection, Rev 0.2, Silicon Laboratories Inc., July, 2013

Title

Field-Programmable Gate Arrays

Book

Building Embedded Systems

Print ISBN: 978-1-4842-1918-8

Electronic ISBN: 978-1-4842-1919-5

https://doi.org/10.1007/978-1-4842-1919-5

DOI

https://doi.org/10.1007/978-1-4842-1919-5_9

Author:

Changyi Gu

Publisher

Apress

Sequence number

Chapter number

Chapter 9